In order for our company to maintain a leadership position in the fast moving technology industry, we are always looking for creative, talented and intelligent people to join our team.

Current Openings

Immediate On-site Verification consulting available:

Immediate opening - location bay area - San Jose CA.

The candidate must have a strong background in developing advanced testbench using system C and Cadence Design Systems (Verisity e) language.

Submit Resume in word format: info@asicip.com

Account Manager

Submit your Resume For information about employment at ASIC IP, please email your resume to iinfo@asicip.com

ASIC (Synthesis, Simulation, Verification, Place and Route, Design Reuse and/or Physical) Design Engineer BS with 3+ years of relevant experience, MS with 5+ years of relevant experience, Knowledge of competitive EDA tool (Synopsys, Magma, Cadence & Mentor) products and product knowledge in any of the areas of Synthesis, Simulation, Verification, Place and Route, Design Reuse and/or Physical Design is highly desired.
send resume to info@asicip.com

Flow Development Engineer

BSEE/MSEE. 5+ years experience developing, implementing, and testing high performance communications and DSP ASIC products. Experience mapping communications algorithms to hardware and understanding of system design tradeoffs for high volume applications. Must have extensive RTL experience including design, verification, and synthesis. Must have strong UNIX-based EDA tool skills and in-depth knowledge of ASIC design flows
send resume to info@asicip.com

Verification Engineer

BS with 3+ years of relevant experience, MS with 5+ years of relevant experience, or related Ph.D. with 3+ years of experience. Good knowledge of high-level design methodologies, strong communication, leadership skills are required. Proficient with C/C++, UNIX, HDL (Verilog/VHDL) and a strong understanding of ASIC design flows. VLSI, and/or CAD engineering. Knowledge of competitive EDA tool products and product knowledge in any of the areas of Synthesis, Simulation, Verification, Place and Route, Design Reuse and/or Physical Design is highly desired.
send resume to info@asicip.com

ASIC Design Engineer

BSEE/MSEE. 8+ years experience designing, implementing, and testing communications and DSP algorithms targeted for ASIC implementation. Experience in mapping communications algorithms to hardware and understanding of system design tradeoffs for high volume applications and debug/test experience using analog and digital bench equipment. DSP firmware implementation (assembly) and 16/32 bit general purpose Microprocessor experience. Experience in RTL design, simulation, and synthesis a plus.

Knowledge of wireline physical layer architectures a plus - particularly echo and crosstalk cancellation techniques. Should have strong presentation and writing skills. UNIX-based EDA tool skills and in-depth knowledge of ASIC design flows a plus. Familiarity with reusable HDL coding styles and design for high volume manufacture a plus. Experience in MATLAB and C/C++ based system simulation and evaluation a plus. Knowledge of gigabit and/or 10 gigabit Ethernet physical layer ASICs a plus.

Consultant and Contactors

Resume submission.....

Submit your Resume For information about employment at ASIC IP, please email your resume to info@asicip.com